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?2006 fairchild semiconductor corporation 1 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series march 2013 FSB32560 motion spm ? 3 series features ? ul certified no.e209204(spm27-bc package) ? 600 v-25 a 3-phase igbt inverter bridge including control ics for gate driving and protection ? three separate negative dc-link terminals for inv erter current sensing applications ? single-grounded power supply for built-in hvic ? isolation rating of 2500 vrms/min. ? very low leakage current by using ceramic substrat e ? rohs compliant applications ? motion control - home appliance/industrial motorfeatures general description FSB32560 is a motion spm? 3 series that fairchild has developed to provide a very compact and high performance inverter solution or ac motor drives in l ow- power applications such as air conditioner. it combi nes optimized circuit protections and drives matched to low-loss igbts. the system reliability is further enhanced by the integrated under-voltage lock-out and over-current protection. the high speed built-in hvic provides optocoupler- less single-supply igbt gate driving capability that further reduces the overall size of the inverter system design. each phase current of inverter can be monitored thanks to the three separate negative dc terminals. resource ? an-9035: motion spm? 3 series ver.2 user's guide package marking and ordering information device marking device package reel size packing type quant ity FSB32560 FSB32560 spmba-027 - rail 10
2 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series integrated power functions ? 600 v-25 a igbt inverter for three-phase dc/ac pow er conversion (please refer to figure 3) integrated drive, protection and system control fun ctions ? for inverter high-side igbts: gate drive circuit, high voltage isolated high-speed level shifting control circuit under-voltage (uv) protection note) available bootstrap circuit example is given in figures 10 and 11. ? for inverter low-side igbts: gate drive circuit, s hort circuit protection (sc) control supply circuit under-voltage (uv) protectio n ? fault sgnaling: corresponding to a uv fault (low-s ide supply) ? input interface: active - high interface, can work with 3.3/5 v logic pin configuration figure 2. (1) v cc(l) (2) com (3) in (ul) (4) in (vl) (5) in (wl) (6) v fo (21) n u (22) n v (23) n w (27) p (15) v b(v) (16) v s(v) (17) in (wh) (18) v cc(wh) (19) v b(w) (20) v s(w) (24) u (25) v (26) w case temperature (t c ) detecting point ceramic substrate (7) c fod (8) c sc (9) in (uh) (10) v cc(uh) (11) v b(u) (12) v s(u) (13) in (vh) (14) v cc(vh) (1) v cc(l) (2) com (3) in (ul) (4) in (vl) (5) in (wl) (6) v fo (21) n u (22) n v (23) n w (27) p (15) v b(v) (16) v s(v) (17) in (wh) (18) v cc(wh) (19) v b(w) (20) v s(w) uv (26) w case temperature (t c ) detecting point ceramic substrate (7) c fod (8) c sc (9) in (uh) (10) v cc(uh) (11) v b(u) (12) v s(u) (13) in (vh) (14) v cc(vh) 13.3 19.1 (1) v cc(l) (2) com (3) in (ul) (4) in (vl) (5) in (wl) (6) v fo (21) n u (22) n v (23) n w (27) p (15) v b(v) (16) v s(v) (17) in (wh) (18) v cc(wh) (19) v b(w) (20) v s(w) (24) u (25) v (26) w case temperature (t c ) detecting point ceramic substrate (7) c fod (8) c sc (9) in (uh) (10) v cc(uh) (11) v b(u) (12) v s(u) (13) in (vh) (14) v cc(vh) (1) v cc(l) (2) com (3) in (ul) (4) in (vl) (5) in (wl) (6) v fo (21) n u (22) n v (23) n w (27) p (15) v b(v) (16) v s(v) (17) in (wh) (18) v cc(wh) (19) v b(w) (20) v s(w) uv (26) w case temperature (t c ) detecting point ceramic substrate (7) c fod (8) c sc (9) in (uh) (10) v cc(uh) (11) v b(u) (12) v s(u) (13) in (vh) (14) v cc(vh) 13.3 19.1 13.3 19.1 top view
3 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series pin descriptions pin number pin name pin description 1 v cc(l) low-side common bias voltage for ic and igbts drivi ng 2 com common supply ground 3 in (ul) signal input for low-side u phase 4 in (vl) signal input for low-side v phase 5 in (wl) signal input for low-side w phase 6 v fo fault output 7 c fod capacitor for fault output duration time selection 8 c sc capacitor (low-pass filter) for short-current detec tion input 9 in (uh) signal input for high-side u phase 10 v cc(uh) high-side bias voltage for u phase ic 11 v b(u) high-side bias voltage for u phase igbt driving 12 v s(u) high-side bias voltage ground for u phase igbt driv ing 13 in (vh) signal input for high-side v phase 14 v cc(vh) high-side bias voltage for v phase ic 15 v b(v) high-side bias voltage for v phase igbt driving 16 v s(v) high-side bias voltage ground for v phase igbt driv ing 17 in (wh) signal input for high-side w phase 18 v cc(wh) high-side bias voltage for w phase ic 19 v b(w) high-side bias voltage for w phase igbt driving 20 v s(w) high-side bias voltage ground for w phase igbt driv ing 21 n u negative dcClink input for u phase 22 n v negative dcClink input for v phase 23 n w negative dcClink input for w phase 24 u output for u phase 25 v output for v phase 26 w output for w phase 27 p positive dcClink input
4 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series internal equivalent circuit and input/output pins note: 1. inverter low-side is composed of three igbts, fr eewheeling diodes for each igbt and one control ic. it has gate drive and protection functions. 2. inverter power side is composed of four inverter dc-link input terminals and three inverter output terminals. 3. inverter high-side is composed of three igbts, f reewheeling diodes and three drive ics for each igb t. figure 3. com vcc in(ul) in(vl) in(wl) vfo c(fod) c(sc) out(ul) out(vl) out(wl) n u (21) n v (22) n w (23) u (24) v (25) w (26) p (27) (20) v s(w) (19) v b(w) (16) v s(v) (15) v b(v) (8) c sc (7) c fod (6) v fo (5) in (wl) (4) in (vl) (3) in (ul) (2) com (1) v cc(l) vcc vb out com vs in vb vs out in com vcc vcc vb out com vs in (18) v cc(wh) (17) in (wh) (14) v cc(vh) (13) in (vh) (12) v s(u) (11) v b(u) (10) v cc(uh) (9) in (uh) v sl
5 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series absolute maximum ratings (t j = 25c, unless otherwise specified) inverter part note: 1. the maximum junction temperature rating of the p ower chips integrated within the spm is 150 c(@t c 100 c). however, to insure safe operation of the spm, t he average junction temperature should be limited to t j(ave) 125 c (@t c 100 c) control part total system thermal resistance note: 2. for the measurement point of case temperature(t c ), please refer to figure 2. symbol parameter conditions rating units v pn supply voltage applied between p- n u , n v , n w 450 v v pn(surge) supply voltage (surge) applied between p- n u , n v , n w 500 v v ces collector-emitter voltage 600 v i c each igbt collector current t c = 25c 25 a t c = 100c 12 a p c collector dissipation t c = 25c per one chip 29 w t j operating junction temperature (note 1) -20 ~ 125 c symbol parameter conditions rating units v cc control supply voltage applied between v cc(uh) , v cc(vh) , v cc(wh) , v cc(l) - com 20 v v bs high-side control bias voltage applied between v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) 20 v v in input signal voltage applied between in (uh) , in (vh) , in (wh) , in (ul) , in (vl) , in (wl) - com -0.3~17 v v fo fault output supply voltage applied between v fo - com -0.3~v cc +0.3 v i fo fault output current sink current at v fo pin 5 ma v sc current sensing input voltage applied between c sc - com -0.3~v cc +0.3 v symbol parameter conditions rating units v pn(prot) self protection supply voltage limit (short circuit protection capability) v cc = v bs = 13.5 ~ 16.5 v t j = 125c, non-repetitive, less than 2 s 400 v t c module case operation temperature -20 c t j 125 c, see figure 2 -20 ~ 100 c t stg storage temperature -40 ~ 125 c v iso isolation voltage 60hz, sinusoidal, ac 1 minute, con nection pins to ceramic substrate 2500 v rms symbol parameter conditions min. typ. max. units r th(j-c)q junction to case thermal resistance inverter igbt part (per 1/6 module) - - 3.5 c/w r th(j-c)f inverter fwd part (per 1/6 module) - - 4.7 c/w
6 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series electrical characteristics (t j = 25c, unless otherwise specified) inverter part note: 3. t on and t off include the propagation delay time of the internal drive ic. t c(on) and t c(off) are the switching time of igbt itself under the gi ven gate driving condition internally. for the detailed information, please see figure 4. figure 4. switching time definition symbol parameter conditions min. typ. max. units v ce(sat) collector-emitter saturation voltage v cc = v bs = 15 v v in = 5 v i c = 25 a, t j = 25c - 2.15 2.85 v v f fwd forward voltage v in = 0 v i c = 25 a, t j = 25c - 2.20 2.90 v hs t on switching times v pn = 300 v, v cc = v bs = 15 v i c = 12 a v in = 0 v ? 5 v, inductive load (note 3) - 0.31 - s t c(on) - 0.15 - s t off - 0.90 - s t c(off) - 0.34 - s t rr - 0.10 - s ls t on v pn = 300 v, v cc = v bs = 15 v i c = 12 a v in = 0 v ? 5 v, inductive load (note 3) - 0.58 - s t c(on) - 0.30 - s t off - 0.96 - s t c(off) - 0.37 - s t rr - 0.10 - s i ces collector-emitter leakage current v ce = v ces - - 250 a v ce i c v in t on t c(on) v in(on) 10% i c 10% v ce 90% i c 100% i c t rr 100% i c 0 v ce i c v in t off t c(off) v in(off) 10% v ce 10% i c (a) turn-on (b) turn-off
7 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series electrical characteristics (t j = 25c, unless otherwise specified) control part note: 4. short-circuit current protection is functioning only at the low-sides. 5. the fault-out pulse width t fod depends on the capacitance value of c fod according to the following approximate equation : c fod = 18.3 x 10 -6 x t fod [f] recommended operating conditions symbol parameter conditions min. typ. max. units i qccl quiescent v cc supply current v cc = 15 v in (ul, vl, wl) = 0v v cc(l) - com - - 23 ma i qcch v cc = 15 v in (uh, vh, wh) = 0v v cc(uh) , v cc(vh) , v cc(wh) - com - - 200 a i qbs quiescent v bs supply current v bs = 15 v in (uh, vh, wh) = 0v v b(u) - v s(u) , v b(v) -v s(v) , v b(w) - v s(w) - - 500 a v foh fault output voltage v sc = 0 v, v fo circuit: 4.7 k to 5 v pull-up 4.5 - - v v fol v sc = 1 v, v fo circuit: 4.7 k to 5 v pull-up - - 0.8 v v sc(ref) short circuit trip level v cc = 15 v (note 4) 0.45 0.5 0.55 v uv ccd supply circuit under- voltage protection detection level 10.7 11.9 13.0 v uv ccr reset level 11.2 12.4 13.2 v uv bsd detection level 10 11 12 v uv bsr reset level 10.5 11.5 12.5 v t fod fault-out pulse width c fod = 33 nf (note 5) 1.0 1.8 - ms v in(on) on threshold voltage applied between in (uh) , in (vh) , in (wh) , in (ul) , in (vl) , in (wl) - com 3.0 - - v v in(off) off threshold voltage - - 0.8 v symbol parameter conditions value units min. typ. max. v pn supply voltage applied between p - n u , n v , n w - 300 400 v v cc control supply voltage applied between v cc(uh) , v cc(vh) , v cc(wh) , v cc(l) - com 13.5 15 16.5 v v bs high-side bias voltage applied between v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) 13.0 15 18.5 v dv cc /dt, dv bs /dt control supply variation -1 - 1 v/ s t dead blanking time for preventing arm-short for each input signal 2.0 - - s f pwm pwm input signal -20 c t c 100c, -20 c t j 125c - - 20 khz v sen voltage for current sensing applied between n u , n v , n w - com (including surge voltage) -4 4 v
8 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series mechanical characteristics and ratings figure 5. flatness measurement position parameter conditions limits units min. typ. max. mounting torque mounting screw: - m3 recommended 0.62 n?m 0.51 0.62 0.72 n?m device flatness note figure 5 0 - +120 m weight - 15.4 - g ( + ) ( + ) ( + ) ( + )
9 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series time charts of spm ? protective function a1 : control supply voltage rises: after the voltag e rises uv ccr , the circuits start to operate when next input is applied. a2 : normal operation: igbt on and carrying current . a3 : under voltage detection (uv ccd ). a4 : igbt off in spite of control input condition. a5 : fault output operation starts. a6 : under voltage reset (uv ccr ). a7 : normal operation: igbt on and carrying current . figure 6. under-voltage protection (low-side) b1 : control supply voltage rises: after the voltag e reaches uv bsr , the circuits start to operate when next input is applied. b2 : normal operation: igbt on and carrying current . b3 : under voltage detection (uv bsd ). b4 : igbt off in spite of control input condition, but there is no fault output signal. b5 : under voltage reset (uv bsr ) b6 : normal operation: igbt on and carrying current figure 7. under-voltage protection (high-side) input signal output current fault output signal control supply voltage reset uv ccr protection circuit state set reset uv ccd a1 a3 a2 a4 a6 a5 a7 input signal output current fault output signal control supply voltage reset uv bsr protection circuit state set reset uv bsd b1 b3 b2 b4 b6 b5 high-level (no fault output)
10 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series (with the external shunt resistance and cr connecti on) c1 : normal operation: igbt on and carrying current . c2 : short circuit current detection (sc trigger). c3 : hard igbt gate interrupt. c4 : igbt turns off. c5 : fault output timer operation starts: the pulse width of the fault output signal is set by the ext ernal capacitor c fo . c6 : input l : igbt off state. c7 : input h: igbt on state, but during the activ e period of fault output the igbt doesnt turn on. c8 : igbt off state figure 8. short-circuit current protection (low-sid e operation only) internal igbt gate-emitter voltage lower arms control input output current sensing voltage of the shunt resistance fault output signal sc reference voltage cr circuit time constant delay sc protection circuit state set reset c6 c7 c3 c2 c1 c8 c4 c5
11 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series note: 1) rc coupling at each input (parts shown dotted) m ight change depending on the pwm control scheme use d in the application and the wiring impedance of th e applications printed circuit board. the spm input signal section integrates 3.3k ( typ.) pull-down resistor. therefore, when using an external filtering resistor, please pay attention t o the sig- nal voltage drop at input terminal. 2) the logic input is compatible with standard cmos or lsttl outputs. figure 9. recommended cpu i/o interface circuit note: 1) it would be recommended that the bootstrap diode , d bs , has soft and fast recovery characteristics. 2) the ceramic capacitor placed between v cc -com should be over 1uf and mounted as close to the pins of the spm as possible. figure 10. recommended bootstrap operation circuit and parameters cpu com 5v-line 1nf 4.7k , , in (ul) in (vl) in (w l) , , in (uh) in (vh) in (w h) v fo 100 1nf spm r pf = c pf = 15v-line 22uf 0.1uf 1000uf 1uf one-leg diagram of spm vcc in com vb ho vs vcc in com out inverter output p n these values depend on pwm control algorithm d bs r bs v sl
12 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series note: 1) to avoid malfunction, the wiring of each input s hould be as short as possible. (less than 2-3cm) 2) by virtue of integrating an application specific type hvic inside the spm, direct coupling to cpu t erminals without any opto-coupler or transformer is olation is possible. 3) v fo output is open collector type. this signal line sh ould be pulled up to the positive side of the 5v po wer supply with approximately 4.7k resistance. please refer to figure 9. 4) c sp15 of around 7 times larger than bootstrap capacitor c bs is recommended. 5) v fo output pulse width should be determined by connect ing an external capacitor(c fod ) between c fod (pin7) and com(pin2). (example : if c fod = 33 nf, then t fo = 1.8ms (typ.)) please refer to the note 5 for calculation method. 6) input signal is high-active type. there is a 3.3 k resistor inside the ic to pull down each input sig nal line to gnd. when employing rc coupling circuit s, set up such rc couple that input signal agree with turn-off/turn-on thres hold voltage. 7) to prevent errors of the protection function, th e wiring around r f and c sc should be as short as possible. 8) in the short-circuit protection circuit, please select the r f c sc time constant in the range 1.5~2 s. 9) each capacitor should be mounted as close to the pins of the spm as possible. 10) to prevent surge destruction, the wiring betwee n the smoothing capacitor and the p&gnd pins should be as short as possible. the use of a high freque ncy non-inductive capacitor of around 0.1~0.22 f between the p&gnd pins is recommended. 11) relays are used at almost every systems of elec trical equipments of home appliances. in these case s, there should be sufficient distance between the cpu and the relays. 12) c spc15 should be over 1 f and mounted as close to the pins of the spm as po ssible. figure 11. typical application circuit fault 15v line c bs c bsc r bs d bs c bs c bsc r bs d bs c bs c bsc r bs d bs c sp15 c spc15 c fod 5v line r pf c bpf r s m vdc c dcs gating uh gating vh gating wh gating wl gating vl gating ul c pf c cc c p pp p u uu u r fu r fv r fw r su r sv r sw c fu c fv c fw w-phase current v-phase current u-phase current r f com vcc in(ul) in(vl) in(wl) vfo c(fod) c(sc) out(ul) out(vl) out(w l) n u (21) n v (22) n w (23) u (24) v (25) w (26) p (27) (20) v s(w ) (19) v b(w ) (16) v s(v) (15) v b(v) (8) c sc (7) c fod (6) v fo (5) in (w l) (4) in (vl) (3) in (ul) (2) com (1) v cc(l) vcc vb out com vs in vb vs out in com vcc vcc vb out com vs in (18) v cc(wh) (17) in (w h) (14) v cc(vh) (13) in (vh) (12) v s(u) (11) v b(u) (10) v cc(uh) (9) in (uh) input signal for short- circ uit protec tion c sc v sl
13 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series detailed package outline drawings
14 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series detailed package outline drawings (continued)
15 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series detailed package outline drawings (continued)
16 www.fairchildsemi.com FSB32560 rev. c01 FSB32560 motion spm ? 3 series

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